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| PAS302BCW-22S cmos image sensor ic v ersion 2.4, 20 sep. 2005 pixart imaging inc. e-mail: fae_service@pixart.com.tw 1 PAS302BCW-22S cmos vga digital image sensor general description the PAS302BCW-22S is a highly integrated cmos active-pixel image sensor that has a vga resolution of 644h x 484v. the PAS302BCW-22S outputs 8-bit rgb raw data through a parallel data bus and is available in 22-pin csp package. the PAS302BCW-22S can be programmed to set the exposure time for different luminance condition via 2tm ic serial control bus. by programming the inter nal register sets, it can perform on-chip frame rate adjustment, offset correction dac and programmable gain control. key specification supply voltage 2.5v ~ 3.3v resolution 644(h) x 484(v) array diagonal 4.5mm (~1/4?optic) pixel size 5.6 mx5.6 m chief ray angle 20 ~ 22 frame rate ~30 fps system clock up to 48 mhz pixel clock up to 12mhz sensitivity 1.56 v/lux-sec color filter rgb bayer pattern exposure time ~ frame time to line time scan mode progressive s/n ratio > 45 db features ? vga(644 x 484 pixels) resolution, ~1/4? lens ? bayer-rgb color filter array ? output format: 8-bit parallel rgb raw data ? on-chip 10-bit pipelined a/d converter ? on-chip programmable gain amplifier ? 4-bit color gain amplifier (x1~x2) ? 4-bit global gain amplifier (x1~x2) ? digital gain stage ? continuous variable frame time(1/2sec~1/30sec) ? continuous variable exposure time ? 2tm ic interface ? support flash light timing ? single 2.5v / 3.3v supply voltage ? < 15ma(~30 fps) power dissipation ? 2a power dissipation when power down mode ? window-of-interest (woi) ? sub-sampling ? defect compensation ? pin-to-pin compatible to ov7648 package 22-pin lead-free csp note1: only two decoupling capacitors needed note2: good sensitivity compared to competitors
PAS302BCW-22S cmos image sensor ic v ersion 2.4, 20 sep. 2005 pixart imaging inc. e-mail: fae_service@pixart.com.tw 2 1. pin assignment 1 " 4 # $ 8 4 1 8 % / 7 4 4 " 7 % % " 7 3 & ' 7 % % % 7 4 : / $ ) 4 : / $ 7 % % 2 1 9 $ - , 3 & 4 & 5 4 : 4 $ - , 4 % " 4 $ - 1 9 1 9 7 4 4 % 1 9 1 9 1 9 1 9 1 9 1 9 -- top view -- figure 1.1. PAS302BCW-22S pin assignment pin no. name type description 1 vssa gnd analog ground 2 vdda pwr analog vdd. 3 pwdn in power down (chip power down when high) 4 vref in internal voltage reference 5 vddd pwr digital vdd. 6 vsync out vertical synchronization signal 7 hsync out horizontal synchronization signal 8 pxclk out pixel clock output 9 vddq pwr sensor vdd, 2.5v ~ 3.3v 10 sysclk in master clock input 11 reset in resets all registers to their default values (chip reset when high) 12 vssd gnd digital ground 13 px9 out digital data out 14 px8 out digital data out 15 px7 out digital data out 16 px6 out digital data out 17 px5 out digital data out 18 px4 out digital data out 19 px3 out digital data out 20 px2 out digital data out 21 scl in 2tm ic clock. 22 sda i/o 2tm ic data. internal pull high resister is 10k ? . PAS302BCW-22S cmos image sensor ic v ersion 2.4, 20 sep. 2005 pixart imaging inc. e-mail: fae_service@pixart.com.tw 3 2. block diagram 4 f o t p s " s s b z y $ % 4 $ p m v n o % f d p e f s 3 p x % f d p e f s ' ( $ ( ( ( # j u " % 5 j n j o h ( f o f s b u p s $ p o u s p m - p h j d % f g f d u $ p n q f o t b u j p o % j h j u b m ( b j o 4 u b h f % " $ % " $ 4 $ - 4 % " 4 : 4 $ - , 7 4 : / $ ) 4 : / $ 1 9 $ - , 1 9 ' s p o u ( b j o $ p m p s ( b j o ( m p c b m ( b j o # j u y _ y # j u y _ y # j u y _ y $ p n q b o e j o h figure 2.1. PAS302BCW-22S sensor block diagram the PAS302BCW-22S is a 1/4? cmos imaging sensor with 644x488 physical pixels. the active region of sensor array is 644x484 as shown in fig. 2.1. the sensor array is covered with bayer pattern color filters and micro-lens. the first pixel location <0,0> is programmable in 2 direction (x and y) and the default value is at the left-down side of sensor array. after a programmable exposure time, the signals of image are sampled first with cds (correlated double sampling) block to improv e s/n ratio and reduce fixed pattern noise. three analog gain stages are implemented before signals are transferred to 10-bit adc. the front gain stage (fg) can be programmed to fit the saturation level of sensor to the full-range input of adc. the programmable color gain stage (cg) is used to balance the luminance response difference between b, g and r color. the global gain stage (gg) is programmed to adapt the gain to the image luminance. after three gain stages, the signals will be digiti zed by the on-chip 10-bit adc. after the image data have been digitized, further adjustment to the signal can be applied before the data is output to next stage. PAS302BCW-22S cmos image sensor ic v ersion 2.4, 20 sep. 2005 pixart imaging inc. e-mail: fae_service@pixart.com.tw 4 3. function description 3.1 defect compensation the defect compensation block can detect the possible defect pixel and replace it with average output of like-colored pixels from near side of defect pixel. there is no limitation capability of defect pixel number. this function can be programmed to enable/disable by user. 3.2 companding curves the companding function which means compressing and expanding is used to simulate the gamma curve and do non-linear transformation before the data is output. there are 4 curves selected by setting register compand_sel as sh own in fig. 3.1. this function can be programmed to enable/disable by user. y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y 0 1 # j u * 1 # j u x j u i p v u d p n q b o e j o h figure 3.1 companding curves programm ed by compand_enh and compand_sel. 3.3 power down mode the PAS302BCW-22S can be powered down by setting register ?sw_pwrdn? = 1 or by enable pwdn pin. the register value will sustain in the power down mode. PAS302BCW-22S supports 2 power down modes: z software power down j set register ?sw_pwrdn? = 1 to power down all the internal block except 2tm ic . z hardware power down j pull pwdn pin to high to power down the chip. the chip will go into standby mode. 3.4 reset mode the PAS302BCW-22S can be reseted by setting register ?sw_reset? = 1 or by enable reset pin. PAS302BCW-22S supports 2 reset modes: z software reset j set register ?sw_reset? = 1 to reset all the 2tm ic registers. z hardware reset j pull reset pin to high to reset the full chip. PAS302BCW-22S cmos image sensor ic v ersion 2.4, 20 sep. 2005 pixart imaging inc. e-mail: fae_service@pixart.com.tw 5 4. output format 4.1 physical sensor array % b s l - j o f % b s l - j o f % b s l - j o f % b s l - j o f 3 p x $ p m v n o 9 " d u j w f 1 j y f m t # # # # # # ( 3 ( ( ( ( ( ( ( ( ( ( 3 3 3 # # # # # # # # ( 3 ( ( ( ( ( ( ( ( ( ( ( 3 3 3 ( 3 ( ( ( ( 3 3 3 3 ( ( ( ( 3 3 3 # # # # ( ( ( # # # 3 ( ( ( ( ( ( ( 3 3 3 3 ( ( ( 3 3 3 # ( ( # # ( figure 4.1 physical sensor array PAS302BCW-22S cmos image sensor ic v ersion 2.4, 20 sep. 2005 pixart imaging inc. e-mail: fae_service@pixart.com.tw 6 4.2 output timing vga mode ( 644 x 488 ) pixel readout: h_start[9:0] = 0, v_start[8:0] = 0, h_size[9:0] = 643, v_size[8:0]= 487, nov_by2[7:0] = 87, ) t z o d / p w 4 j [ f / p w @ # z 1 j y d m l t e f g b v m u - j o f u j n f / p w 4 j [ f 1 j y d m l t e f g b v m u 7 b m j e q j y f m 1 j y d m l t # # # # ( ( ( ( ( ( ( ( 3 3 3 3 / p w 4 j [ f 1 j y d m l figure 4.2 inter-line timing ( default ) if mask_dark[3] = 0, 7 t z o d ) t z o d % b s l % b s l % b s l % b s l % b s l ' s b n f 5 j n f - 1 ' - j o f e f g b v m u % b s l - j o f - j o f 7 b m j e - j o f - j o f figure 4.3 inter-frame timing (lpf default setting = 487, mask_dark[3] =0) if mask_dark[3] = 1, 7 t z o d ) t z o d ' s b n f 5 j n f - 1 ' - j o f e f g b v m u 7 b m j e - j o f - j o f % b s l - j o f - j o f figure 4.4 inter-frame timing (lpf default setting = 487, mask_dark[3] =1) 4.3 hardware windowing users are allowed to define window size as well as window location in PAS302BCW-22S, window size can range from 20x14 to 644x484. the location of window can be anywhere in the sensor array. window location and size is defined by register h_start, v_start, h_size and v_size; the h_start defines the starting column while v_start defines the starting row of the window; the h_size define the column width of the window and v_start define the row depth of the window. 4.4 sub-sampling PAS302BCW-22S can be programmed to output im age in qvga and qqvga size by setting registers skip_digital or skip_analog. in qvga sub-sampling mode, both vertical and horizontal pixels are sub-sampling at 1/2, wh ile in qqvga sub-sampling mode, both vertical and horizontal pixels are sub-sampling at 1/ 4. the maximum sub-sampling rate is 1/16. PAS302BCW-22S cmos image sensor ic v ersion 2.4, 20 sep. 2005 pixart imaging inc. e-mail: fae_service@pixart.com.tw 7 5. 2tm ic bus PAS302BCW-22S supports 2tm ic bus transfer protocol and acts as slave device. the 7 bits unique slave address is 1000000 and the bus sup ports receiving / transmitting speed up to 400khz. 5.1 2tm ic bus overview there are only two lines sda (serial data) and scl (serial clock) carry information between the devices which are connected by 2tm ic bus. normally both sda and scl lines are open collector structure and pulled high by external pull-up resistors. only the master can initiate a transfer (start ), generate clock signals, and terminate a transfer (stop). start condition : a high to low transition of the sda line while scl is high defines a start condition. stop condition : a low to high transition of the sda line while scl is high defines a stop condition. valid data: the data on the sda line must be stable during the high period of the scl clock. within each byte, msb is always transferred first. read/writ e control bit is the lsb of the first byte. both the master and slave can transmit and receive data from the bus. acknowledge : the receiving device should pull down the sda line during high period of the scl clock line when a byte was transferred completely by tr ansmitter. when in the case of that a master received data from a slave, the master does not generate an acknowledgment on the last byte to indicate the end of a master read cycle. figure 5-1: start and stop conditions figure 5-2: valid data data stable data change allowed sda scl 4 4 u b s u $ p o e j u j p o 4 % " 4 $ - 1 4 u p q $ p o e j u j p o PAS302BCW-22S cmos image sensor ic v ersion 2.4, 20 sep. 2005 pixart imaging inc. e-mail: fae_service@pixart.com.tw 8 5.2 data transfer format 5.2.1 master transmits data to slave (write cycle) ? s : start ? a : acknowledge by slave ? p : stop ? rw : the lsb of 1st byte to decide whether current cycle is read or write cycle. if rw=1 that means read cy cle, if rw=0 that means write cycle. ? subaddress : the address values of PAS302BCW-22S internal control registers (please refer to PAS302BCW-22S register description) during the write cycle, the master generates start condition and then places the 1st byte data that combined slave address (7 bits) with a read/write control bit on sda line. after slave(PAS302BCW-22S) issues acknowledgment, the master places 2nd byte (sub-address) data on sda line. and then following the slave?s( PAS302BCW-22S) acknowledgment, the master places the 8 bits data on sda line and tr ansmit to PAS302BCW-22S control register (address was assigned by 2nd byte). after PAS302BCW-22S issue acknowledgment, the master can generate a stop condition to end this wr ite cycle. in the condition of multi-byte write, the PAS302BCW-22S sub-address will be increase d automatically after each data byte has been transferred. the data and a cycles are repeat ed until last byte write. every control registers value inside PAS302BCW-22S can be pr ogramming via this way. (please refer to figure 5.3.) 5.2.2 slave transmits data to master (read cycle) ? the sub-address was assigned by previous write cycle ? the sub-address is automatically increased after each byte read ? am : acknowledged by master ? note: there is no acknowledgment from master after last byte read during read cycle, the master generates start co ndition and then place the 1st byte data that combine slave address (7 bits) with a read/writ e control bit to sda line. after slave issue acknowledgment, 8 bits data was placed on sda line by PAS302BCW-22S. the 8 bit data was read from PAS302BCW-22S internal control re gister that address was assigned by previous write cycle. following the master acknowledgme nt, the PAS302BCW-22S place the next 8 bits data (address is increased automatically) on sda line and then transfer to master serially. the s slave address (7 bits) rw a data (8 bit) am data 1 p 1st byte 2nd byte n byte no ack in last byte am data s slave id (7 bit) rw a subaddress (8 bit) a data p a 1st byte 2nd byte n bytes + a msb lsb=0 a data PAS302BCW-22S cmos image sensor ic v ersion 2.4, 20 sep. 2005 pixart imaging inc. e-mail: fae_service@pixart.com.tw 9 data and am cycles are repeated until the last byte read. after last byte read, am is no longer generated by master but instead of keeping sda line as high. the slave (PAS302BCW-22S) must releases sda line back to master to generate stop condition. (please refer to figure 5.3.) figure 5.3 data transfer format 5.3 2tm ic bus timing figure 5.4 2tm ic bus timing 5.4 2tm ic bus timing specification standard-mode parameter symbol min. max. unit scl clock frequency f scl 10 400 khz hold time (repeated) start condition. a fter this period, the first clock pulse is generated. t hd:sta 4.0 - s low period of the scl clock t low 4.7 - s high period of the scl clock t high 0.75 - s set-up time for a repeated start condition t su;sta 4.7 - s data hold time. for 2tm ic bus device t hd;dat 0 3.45 s data set-up time t su;dat 250 - ns rise time of both sda and scl signals(note) t r 30 n.d. ns fall time of both sda and scl signals(note) t f 30 n.d. ns set-up time for stop condition t su;sto 4.0 - s bus free time between a stop and start t buf 4.7 - s capacitive load for each bus line c b 1 15 pf 4 % " 4 $ - u g u ) % 4 5 " u - 0 8 u s u ) % % " 5 u ) * ( ) u 4 6 % " 5 u g u 4 6 4 5 " u ) % 4 5 " u 4 1 u 4 6 4 5 0 u # 6 ' u s 1 4 4 s 4 4 % " 4 $ - 4 4 u b s u $ p o e j u j p o 1 4 u p q $ p o e j u j p o " $ , g s p n 3 f d f j w f s % b u b " $ , g s p n 3 f d f j w f s % b u b " $ , g s p n 3 f d f j w f s 3 8 " e e s f t t PAS302BCW-22S cmos image sensor ic v ersion 2.4, 20 sep. 2005 pixart imaging inc. e-mail: fae_service@pixart.com.tw 10 noise margin at low level for each connected device (including hysteresis) v nl 0.1 vdd - v noise margin at high level for each connected device (including hysteresis) v nh 0.2 vdd - v note: it depends on the "high" period time of scl. PAS302BCW-22S cmos image sensor ic v ersion 2.4, 20 sep. 2005 pixart imaging inc. e-mail: fae_service@pixart.com.tw 11 6. electrical characteristics absolute maximum ratings ambient storage temperature -40 ~ +125 v ddd 3v v dda 3v v ddma 4v supply voltages ( with respect to ground ) v ddq 4v all input / output voltages ( with respect to ground ) -0.3v to v ddq + 1v lead temperature, surface-mount process +230 esd rating, human body model 2000v dc electrical characteristics ( vdd = 2.5v 4% , ta = 0 ~ 70 ) symbol parameter min. typ. max. unit type :pwr v dda dc supply voltage ? analog 2.4 2.5 2.6 v v ddd dc supply voltage ? digital 2.4 2.5 2.6 v v ddq dc supply voltage ? i/o 2.4 - 3.3 v i dd operating current 15 ma i pwdn power down current 2 a type :in & i/o reset and sysclk v ih input voltage high 0.7 x v ddq v v il input voltage low 0.3 x v ddq v c in input capacitor 10 pf type : out & i/o for pxd0:7, pxck, h/vsync & sda, load 10pf, 1.2k ? , 2.5volts v oh output voltage high 0.9 x v ddq v v ol output voltage low 0.1 x v ddq v ac operating condition symbol parameter min. typ. max. unit sysclk master clock frequency 48 mhz pxck pixel clock output frequency 12 mhz sensor characteristics parameter typ. unit note sensitivity 1.56 v/lux-sec signal to noise ratio > 45 db dynamic range 60 db operation -10 ~ 70 temperature range stable image 0 ~ 50 PAS302BCW-22S cmos image sensor ic v ersion 2.4, 20 sep. 2005 pixart imaging inc. e-mail: fae_service@pixart.com.tw 12 7. reference circuit schematic pas302bcw u1 px7 15 px6 16 px5 17 px4 18 pwdn 3 scl 21 vssa 1 sda 22 vdda 2 vref 4 vddd 5 vsync 6 hsync 7 pxclk 8 vddq 9 sy sclk 10 reset 11 vssd 12 px9 13 px8 14 px3 19 px2 20 pxclk sy sclk pwdn sda scl vref hsync vsync vddq px8 reset px9 px4 px7 px5 vsy nc hsync pxclk px2 px7 sda sy sclk scl px3 px6 jp1 sensor board interface 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 px8 pwdn px9 px6 px5 vddq px4 px3 px2 c2 0.1u notes: vddq is 2.5v to 3.3v sensor power. c1 should close to sensor vdda and agnd. c2 should close to sensor vref and agnd. c1 0.1u reset PAS302BCW-22S cmos image sensor ic v ersion 2.4, 20 sep. 2005 pixart imaging inc. e-mail: fae_service@pixart.com.tw 13 8. package specification dimensions symbol min. typ. max. unit package body dimension x a 4310 4335 4360 m package body dimension y b 4130 4155 4180 m package height c 740 800 860 m ball height c1 130 160 190 m package body thickness c2 605 640 675 m thickness of glass surface to wafer c3 395 415 435 m ball diameter d 270 300 330 m pin pitch x axis j1 - 800 - m pin pitch y axis j2 - 800 - m edge to pin center distance along x s1 537.5 567.5 597.5 m edge to pin center distance along y s2 447.5 477.5 507.5 m PAS302BCW-22S cmos image sensor ic v ersion 2.4, 20 sep. 2005 pixart imaging inc. e-mail: fae_service@pixart.com.tw 14 9. recommended lens and holder PAS302BCW-22S cmos image sensor ic v ersion 2.4, 20 sep. 2005 pixart imaging inc. e-mail: fae_service@pixart.com.tw 15 |
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